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[编者注： 一个系统的设计和演化是非常好玩的。这个是 intel fellow Glenn Hinton 在 Stanford 给的一个talk. 他讲了在设计 Nehalem Core 的时候面对以及做出了什么样的设计选择. 我们可以看到一个通用CPU在设计的时候会面临什么样的需求.  在这个slide 里边他主要谈到了 core 部分的设计，并没有忽悠 memory controller & QPI. 从这个 slides 里边我们可以看到

*Nehalem core 为什么 based on P6 放弃了 netburst.

*Nehalem core 为什么引入了 Turbo mode.

*Power efficiency design 成为了一个主轴.

*Nehalem core 为什么把 SMT 搞回来。

Nehalem core 也引入了 L2 TLB。 有一个好玩的地方是在slide中我们看到 nehalem  LOCK CMPXCHG 的 latency减少了很多。这个应该是归功于 Nehalem 在 L3 cache line 里边引入了类似 directory cache coherent protocol 的优化措施。Cache line 上 有 bit 来表明数据在 各个 core 的分布情况.

对于 SMT, 我们发现很多应用并不能从 SMT 上得到什么好处。L1 cache & TLB 的 contention 非常强烈。 要想从SMT中得到加速，需要码农们仔细优化一下程序。

另外推荐这个 http://www.stanford.edu/class/ee380/ 。 里边很多很好的 talk。 slides 下下来看看，也花不了很多时间。

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About the speaker:

Glenn Hinton is an Intel Fellow who was the lead architect of the Nehalem CPU development at Intel. He also lead the micro-architecture development for the Intel� Pentium 4 processor beginning in 1995. He was one of the 3 senior architects of the P6 processor design that started in 1990. This became the Intel� Pentium� Pro, Intel� Pentium� II, and Intel� Pentium� III processors and is the base pipeline for the Intel� Core and Nehalem family of CPUs. In 1986 he was one of the two lead micro-architects of the i960� CA, which was the world’s first super-scalar microprocessor. He has been at Intel for 27 years. He holds more than 90 patents from 8 different CPU designs. He received the ACM Maurice Wilkes Award in 2002. Hinton received bachelor’s and master’s degrees in electrical engineering from Brigham Young University in 1982 and 1983, respectively.

Link address

http://www.stanford.edu/class/ee380/Abstracts/100217-slides.pdf

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