FP2网络处理器架构师Clarke的设计理念  

New Case for a Programmable Fastpath 

转载自 

http://www.eetimes.com/design/programmable-logic/4008959/New-Case-for-a-Programmable-Fastpath 

Michael Clarke is a network processor architect at TiMetra Networks. He holds an MA in Engineering from Cambridge University, UK. 

7年前的文章，放到今天仍不过时。Alcatel收购Timetra团队真是不错的Deal。该团队从Treseq/Bay/Nortel积累了一批高手。 

该文章信息量大，内容丰富。从中可以看出FP1、FP2网络处理器的架构设计理念。 

摘录出下述关键内容：  

Increased packet rates and the relatively long latencies of modern RAM technologies require that an ever-increasing number of packets be processed simultaneously. 

包速率高，RAM访问的时延大，故需要很多包并行处理。提高并行处理的包数目有两个方法：增加硬件线程数目；或者用Pipeline Stage。Timetra是用后者。 

NPUs facilitate a number of generic lookup types, such as direct lookups, hash lookups, radix trie lookups, and CAM lookups. The size of the tables and the contents of the table entries and CAM keys are entirely defined in firmware. 

查表要可编程。故IPv4 FIB等查表TRIE算法应该是用微码实现，而不是用硬件实现。这与思科思路不同，思科的Tree bitmap介绍是用硬件实现，而不是NPU的微码实现。 

To provide sufficient processing power, NPUs use the fact that packets can be processed largely independently of one another. NPUs typically have multiple processor cores and a number of packets are processed in parallel or in a pipelined fashion. A great deal of effort can be focused on designing the individual processor cores, making them as speed, area and power efficient as possible. These optimized designs can then be replicated many times, reducing the overall implementation effort for a large proportion of the silicon area of the NPU. 

专注于将每个Core在性能、面积和功耗上优化，优化后的Core可以以并行或串行的方式重复放很多次。 

Because the performance of a single thread is not as critical in NPUs as in traditional CPUs, using additional silicon area to provide increased processor performance must be weighed against simply using the extra silicon area to add more processor cores. 

花更大的代价将每个CORE做得很强，还是用同样的成本放更多的CORE。偏向于后者。 

Table memories are not necessarily cached because the design will be expected to work at line-rate with any combination of input packets and must take into consideration the worst-case latency to random table entries. 

外部表项线速查表，不用Cache。这与思科思路不同：查表会用上Cache。 

Performance is now determined by instruction counts and lookup bandwidth. 

NPU的整体表现是由两个指标决定：处理指令数目，查表次数。 

between 100 and 1000 instructions can be executed for each packet. 

处理性能：NPU对一个包大概可以执行100至1000条指令。 

Typical fastpath programs make between 20 and 80 lookup table accesses per packet to implement a meaningful feature set 

一个Packet要有20至80次查表机会，以便于业务扩展 

Also, programs are heavily tied to the NPU’s specific hardware resources. Hence the requirement to support legacy code is not as strong for NPUs as it is for general purpose CPUs, and this affords the designer some freedom to implement novel architectures NPU是专用芯片，它无须支持传统的编程语言，而可以选择自己的ISA结构，以充分提高处理性能。这与思科的思想不一样，思科坚持用C语言编程。 

Essentially NPUs execute many bit level compares and moves, interspersed with regular computation of table entry addresses for lookups.  The mix of instructions in a typical application differs between NPUs and CPUs and this must be taken into account when assessing the effectiveness of alternative architectures. 

NPU涉及大量的位域比较操作，故其指令集与通用CPU有所不同。思科是使用标准的Tensilica指令集。 

Sufficient bandwidth for lookups must also be provided and the right balance must be struck between processing power and lookup bandwidth。 

NPU处理性能与查表带宽之间要取得一个平衡。 

NPUs may also be cascaded to provide additional processing performance and lookup bandwidth. 

NPU可以级联起来，以提供更强的处理能力和更多的查表带宽。IOM2/IOM3正是这样做的。 

New Case for a Programmable Fastpath

Kevin Macaluso and Michael Clarke, TiMetra Networks

5/15/2003 6:14 AM EDT

• Lookups for Layer 2 services, including source and destination MAC addresses
• Mapping to an egress port within a link aggregation group (LAG)
• Layer 3 lookups to determine classless inter-domain routing (CIDR) and equal-cost multipath (ECMP) load balancing next hops
• Searching access control list (ACL) filters and quality-of-service (QoS) policies based on IP and TCP header fields.

Many additional complexities arise, such as the location of fields in the packet varying depending on whether 802.1q tags or MPLS encapsulations are present. IP fragmentation may have to be performed to meet the MTU requirements of the destination interface.The results of the lookups are combined to determine how the packet should be directed through the switch fabric and its queuing requirements, such as forwarding class and QoS. Implementations tend to prepend this information to the packet in the form of a routing tag. The packet itself may have to be modified in different ways, ranging from simply decrementing the IP TTL field, to encapsulation with a multiprotocol label switching (MPLS) header. Statistics counters need to be maintained and traffic policing functions may have to be performed.Traditional Implementations
The traditional approach to fastpath implementation involves identifying all of the possible packet classification and manipulation requirements and committing them to silicon. This was done in previous generations of routers because these tasks were more readily defined and ASICs were relatively inexpensive to spin by today’s standards. Additionally, there simply wasn’t any spare area afforded by the silicon processes available at the time to do things differently. This approach also demands that crucial design decisions are made early in the development cycle. Packet formats, lookup table entries, and content-addressable memory (CAM) lookup keys all have to be defined. Resources such as internal and external RAMs and CAMs are selected and sized based on bandwidth and scalability requirements. A certain amount of configurability is implemented to mitigate against anticipated future requirements, such as providing facilities to turn individual features on or off, or to choose between subtle variations of a feature.A fundamental deficiency in the traditional approach is that protocols not considered or defined at this stage cannot be supported later on without new silicon. Arising problems, such as unforeseen interoperability issues, may also not be able to be satisfactorily resolved without new silicon. Some support for resizing tables may also be provided but can prove limiting if applications with unconventionally large table requirements are to be supported.Once the packet and table formats have been defined, accesses to resources are scheduled and the flow of packets through the device is arranged. This is achieved by considering the latency of the memories employed and the interdependencies of the lookups.Increased packet rates and the relatively long latencies of modern RAM technologies require that an ever-increasing number of packets be processed simultaneously. Straightforward deterministic scheduling of accesses to resources is complicated by non-deterministic lookups such as descending through a hash chain. Arbiters may have to be designed to handle cases where multiple state machines simultaneously require access to a shared resource. Counters and policers require atomic access to table entries. Rather than designing generic mechanisms to address these problems, optimized schemes for each operation are usually employed. Handling the complexity of such a design is difficult.As with any silicon design, the consequences of errors are significant. Small anomalies in the implementation of features can make those features unusable in production networks. A high-level engineering approach can be employed to achieve a high quality result by rigorously abstracting the definition of the packet and table formats and lookup algorithms from the detailed hardware designThere are two major benefits to this traditional approach to fastpath design. First, designs can be very efficient in terms of silicon area and power consumption. Second, because the precise arrangement of table accesses is known in advance, it is relatively straightforward to ensure that such a solution will perform at line-rate for a given set of enabled features.Making the Move to NPUs
In making the move from traditional ASIC-based approaches to programmable NPUs, designers must resolve the deficiencies of traditional approaches and achieve the same performance as a hardwired fastpath, while providing an order of magnitude increase (at least) in flexibility. The size and function of the lookup tables should be fully programmable. Any type of packet manipulation must be possible, including generically replacing large quantities of the packet with data derived from lookups.Solutions range from embedding FPGA-like regions into an ASIC, to the currently favored solution of NPUs. NPUs comprise a number of true processor cores, using an execution pipeline driven from an instruction set that is highly optimized for networking applications. While NPUs utilize silicon area less efficiently than a hardwired solution, they are not unreasonably inefficient when compared with the area of traditional packet handling logic and associated table memories.To provide sufficient processing power, NPUs use the fact that packets can be processed largely independently of one another. NPUs typically have multiple processor cores and a number of packets are processed in parallel or in a pipelined fashion. A great deal of effort can be focused on designing the individual processor cores, making them as speed, area and power efficient as possible. These optimized designs can then be replicated many times, reducing the overall implementation effort for a large proportion of the silicon area of the NPU.Another characteristic that distinguishes NPUs from a general-purpose processor is the inclusion of hardware to assist in passing packets from dedicated packet interfaces to the processor cores with very low processor overhead. The processor cores typically have very low latency and highly flexible access to the packets they are processing.NPUs facilitate a number of generic lookup types, such as direct lookups, hash lookups, radix trie lookups, and CAM lookups. The size of the tables and the contents of the table entries and CAM keys are entirely defined in firmware. Both internal and external memories may be provided for storing tables. Multiple external interfaces are provided to specific devices such as SDRAMs, SRAMs and CAMs, as well as in the form of generic lookaside interfaces.Table memories are not necessarily cached because the design will be expected to work at line-rate with any combination of input packets and must take into consideration the worst-case latency to random table entries. For the same reason SRAMs tend to be favored over SDRAMs for storing tables to avoid the bank-to-same-bank access latencies of SDRAMs.Double-data-rate (DDR) SRAMs may be preferred for tables where the processor is mainly reading, while quad-data-rate (QDR) SRAMs may be preferred for features like statistics counters, where there is an even balance between reads and writes. For ACL and QoS IP and TCP header lookups, or other n-tuple lookups where a number of independent fields are to be classified, ternary CAMs (TCAMs) may be employed.Design Tradeoffs
Trade-offs must still be made in the design of the NPU that will affect its ultimate flexibility and performance. Performance is now determined by instruction counts and lookup bandwidth.There are many options for differentiation in the design of the processor cores. A 10 Gigabit Ethernet interface has a worst-case packet arrival rate of 15 million packets per second (Mpps). Assuming a processor clock frequency between 100 and 1000 MHz and the number of processor cores being between 16 and 64, and taking power limitations into account, between 100 and 1000 instructions can be executed for each packet.Off-the-shelf instruction sets could be used or extended. With such a small number of instructions that can be executed for each packet, the overall size of programs is correspondingly small. Also, programs are heavily tied to the NPU’s specific hardware resources. Hence the requirement to support legacy code is not as strong for NPUs as it is for general purpose CPUs, and this affords the designer some freedom to implement novel architectures in an attempt to close the efficiency gap between a hardwired and a processor-based solution.Essentially NPUs execute many bit level compares and moves, interspersed with regular computation of table entry addresses for lookups. Examples include manipulating fields in tightly packed table entries and selecting packet fields for inclusion in a CAM lookup key.Increasing the effectiveness of individual instructions and increasing the average number of instructions executed per clock cycle are two ways of improving performance in processors for a given clock frequency, so alternatives such as heavy microcoding and VLIW-style fetching of two instructions per clock cycle may be considered. Solutions akin to those used in DSPs, such as incorporating very specialized instructions for comparing multiple fields simultaneously, may also be considered. The mix of instructions in a typical application differs between NPUs and CPUs and this must be taken into account when assessing the effectiveness of alternative architectures. As broad a range as possible of NPU applications, such as both IP and ATM forwarding, must be considered.A strength of RISC-based architectures that must be maintained is that as many functional units as possible are kept fully utilized in typical code flows. Because the performance of a single thread is not as critical in NPUs as in traditional CPUs, using additional silicon area to provide increased processor performance must be weighed against simply using the extra silicon area to add more processor cores.Sufficient bandwidth for lookups must also be provided and the right balance must be struck between processing power and lookup bandwidth. Typical fastpath programs make between 20 and 80 lookup table accesses per packet to implement a meaningful feature set. Multiple requests to shared resources will be outstanding simultaneously. This can be addressed in hardware by enforcing fairness between requesters and in firmware by ensuring that the bandwidth of individual resources is not exceeded.Service routers generally require more complex algorithms than traditional router applications. Enough overhead must be provided at the hardware design stage for future feature and scalability requirements. NPUs can be scaled by adding special purpose peripheral chips that attach to the NPU using its lookaside bus to provide additional features. NPUs may also be cascaded to provide additional processing performance and lookup bandwidth.Tools Start Answering the Call
Critics often say that NPUs are difficult to program. This is because complex design decisions still exist. Previously, hardware designers were solely involved with scheduling accesses to resources such as table memories. Now this is encompassed by the firmware.The tools used to develop the firmware for NPUs now contribute to the effectiveness of the solution. These tools can present a simplified and single threaded programming model for the processor array. They can help with managing packet and table format definitions throughout the system and with scheduling accesses to resources. Protocol design can be abstracted further from the hardware, in contrast to a traditional fastpath implementation where the protocol design and the hardware design are considered simultaneously.Queuing/Switch Fabric Access
While the NPU’s packet classification and manipulation functions form the heart of a programmable fastpath, a complete forwarding-plane solution also requires queuing and, in the case of a system with multiple linecards and a switch fabric, interfacing to the switch fabric through a backplane. A traffic management (TM) device that implements the QoS policies determined by the NPU performs the queuing function.Queuing in a service router is more demanding than in a traditional router. Tens of thousands of queues have to be supported because each service is queued separately. In fact, each service may have multiple queues allocated to it. Each queue has an independent PIR shaper and CIR marker in order to provide SLA-based services.Such queuing operations involve very specialized atomic operations on large amounts of data and as such are unsuitable for implementation using a processor array. The goal is for the NPU to retain detailed control over how the TM queues its packets, thus the NPU selects destination queues, forwarding classes, drop preferences, and other such parameters.Benefits of a Programmable Fastpath
There are already real-world examples that demonstrate the benefits of NPU flexibility. Recently, the draft-Martini encapsulation was adopted for virtual private LAN service (VPLS). Moving away from a pre-standard or proprietary encapsulation for transparent LAN services to support this emerging standard would have been impossible in a fully hardwired design. In contrast, NPU-based solutions would require relatively straightforward modifications to header formats and suitable changes to the program flow.Another benefit of NPU flexibility is that it allows for a phased implementation of complex features that are currently not broad market requirements but may become so in the future. Instead of having to devote resources and intellectual effort to providing a service now, such as hardwired IPv6 routing, a vendor can ship hardware that is guaranteed to be upgradeable in the field via microcode to support IPv6 routing in the future. Time to market for new features is improved, as is flexibility in meeting specific market and customer demand.Service routers enable providers to consolidate a broad range of revenue-generating services onto a common IP/MPLS infrastructure and support new service offerings that enhance their competitive position in the market. Deploying service routers that use a programmable 10-Gbit/s fastpath benefits service providers in the following ways:

• Reduces CAPEX by adding features into the fastpath without hardware (I/O module) replacement
• Reduces operational disruption and delivers significant OPEX savings by eliminating truck rolls for new feature upgrades
• Enables faster time-to-market for new features and services because developing firmware is months faster than spinning ASICs
• Offers ATM-like QoS capabilities for SLA-based services over IP/MPLS networks
• Delivers any service at any speed on any port — contrasting feature-specific I/O modules with varying performance depending on ASIC version and features required

With the availability of both fully programmable 10 Gbit/s NPUs and TMs that support per-service queuing, the new generation of service routers that are now being deployed will help carriers satisfy customer demand for a wide range of cost-effective, SLA-based data services over IP/MPLS.About the Authors